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19-1687; Rev 1; 7/00
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
General Description
The MAX1284/MAX1285 12-bit analog-to-digital converters (ADCs) combine a high-bandwidth track/hold (T/H), a serial interface with high conversion speed, an internal +2.5V reference, and low power consumption. The MAX1284 operates from a single +4.5V to +5.5V supply. The MAX1285 operates from a single +2.7V to +3.6V supply. The 3-wire serial interface connects directly to SPITM/QSPITM/ MICROWIRETM devices without external logic. The devices use an external serial-interface clock to perform successive-approximation analog-to-digital conversions. Low power, ease of use, and small package size make these converters ideal for remote-sensor and data-acquisition applications or for other circuits with demanding power consumption and space requirements. The MAX1284/MAX1285 are available in 8-pin SO packages. These devices are pin-compatible, higher-speed versions of the MAX1240/MAX1241. Refer to the respective data sheets for more information.
____________________________Features
o Single-Supply Operation +4.5V to +5.5V (MAX1284) +2.7V to +3.6V (MAX1285) o 1LSB (max) DNL, 1LSB (max) INL o 400ksps Sampling Rate (MAX1284) o Internal Track/Hold o +2.5V Internal Reference o Low Power: 2.5mA (400ksps) o SPI/QSPI/MICROWIRE 3-Wire Serial-Interface o Pin-Compatible, High-Speed Upgrades to MAX1240/MAX1241 o 8-Pin SO Package
MAX1284/MAX1285
Ordering Information
PART MAX1284BCSA MAX1285BCSA TEMP. RANGE 0C to +70C 0C to +70C PINSUPPLY PACKAGE VOLTAGE (V) 8 SO 8 SO 5 5 2.7 to 3.6 2.7 to 3.6
Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Pen Digitizers Process Control
MAX1284BESA* -40C to +85C 8 SO MAX1285BESA -40C to +85C 8 SO *Future product--contact factory for availability.
Pin Configuration
TOP VIEW
VDD AIN 1 2 8 7 SCLK CS DOUT GND SHDN CS SCLK 7 8 3 CONTROL LOGIC
Functional Diagram
VDD 1
SHDN 3 REF 4
MAX1284 MAX1285
6 5
INT CLOCK
OUTPUT SHIFT REGISTER
6
DOUT
SO
AIN
2
T/H
12-BIT SAR
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REF
+2.5V REFERENCE 4 5 GND
MAX1284 MAX1285
________________________________________________________________ Maxim Integrated Products
1
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V AIN to GND................................................-0.3V to (VDD + 0.3V) REF to GND ...............................................-0.3V to (VDD + 0.3V) Digital Inputs to GND...............................................-0.3V to +6V DOUT to GND............................................-0.3V to (VDD + 0.3V) DOUT Current ..................................................................25mA Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.88mW/C above +70C) ..............471mW Operating Temperature Ranges MAX1284BCSA/MAX1285BCSA .......................0C to +70C MAX1284BESA/MAX1285BESA .....................-40C to +85C Storage Temperature Range............................-60C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX1284
(VDD = +4.5V to +5.5V; fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7F capacitor at REF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Error Temperature Coefficient DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5Vp-p, clock = 6.4MHz) Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note 4) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUT (AIN) Input Voltage Range Input Capacitance VAIN 0 18 2.5 V pF tSCLK 0.5 40 tCONV tACQ 10 <50 6.4 60 2.5 468 s ns ns ps MHz % SINAD THD SFDR IMD fIN1 = 99Hz, fIN2 = 102Hz -3dB point SINAD > 68dB Up to the 5th harmonic 70 -80 80 76 6 350 dB dB dB dB MHz kHz 0.8 INL DNL No missing codes over temperature 12 1.0 1.0 6.0 6.0 Bits LSB LSB LSB LSB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS--MAX1284 (continued)
(VDD = +4.5V to +5.5V; fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7F capacitor at REF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Output Tempco Load Regulation (Note 5) Capacitive Bypass at REF DIGITAL INPUTS (SCLK, CS, SHDN) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUT (DOUT) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER SUPPLY Positive Supply Voltage (Note 6) Positive Supply Current (Note 7) Shutdown Supply Current Power-Supply Rejection VDD IDD ISHDN PSR VDD = +5.5V SCLK = VDD, SHDN = GND VDD = +5V 10%, midscale input 4.5 2.5 2 0.5 5.5 4.0 10 2.0 V mA A mV VINH VINL VHYST IIN CIN VOL VOH IL COUT ISINK = 5mA ISOURCE = 1mA CS = +5V CS = +5V 15 4 10 VIN = 0 or VDD 15 0.4 0.2 1 3.0 0.8 V V V A pF V V A pF TC VREF 0 to 1mA output load 4.7 VREF TA = +25C 2.48 2.50 30 15 0.1 2.0 10 2.52 V mA ppm/C mV/mA F SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1284/MAX1285
ELECTRICAL CHARACTERISTICS--MAX1285
(VDD = +2.7V to +3.6V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7F capacitor at REF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Error Temperature Coefficient 1.6 INL DNL No missing codes over temperature 12 1.0 1.0 6.0 6.0 Bits LSB LSB LSB LSB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
ELECTRICAL CHARACTERISTICS--MAX1285 (continued)
(VDD = +2.7V to +3.0V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7F capacitor at REF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note 4) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUT (AIN) Input Voltage Range Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Output Tempco Load Regulation (Note 5) Capacitive Bypass at REF DIGITAL INPUTS (SCLK, CS, SHDN) Input High Voltage VINH Input Low Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUT (DOUT) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER SUPPLY Positive Supply Voltage (Note 6) Positive Supply Current (Note 7) Shutdown Supply Current Power-Supply Rejection VDD IDD ISHDN PSR 2.7 VDD = +3.6V SCLK = VDD, SHDN = GND VDD = +2.7V to 3.6V, midscale input 2.5 2 0.5 3.6 3.5 10 2.0 V mA A mV VINL VHYST IIN CIN VOL VOH IL COUT VIN = 0 or VDD 15 ISINK = 5mA ISOURCE = 0.5mA CS = +3V CS = +3V 4 10 15 0.4 0.2 1 VREF TA = +25C TC VREF 0 to 0.75mA output load 4.7 2.0 0.8 2.48 2.50 15 15 0.1 2.0 10 2.52 V mA ppm/C mV/mA F V V V A pF V V A pF VAIN 0 18 2.5 V pF tSCLK 0.5 40 tCONV tACQ 10 <50 4.8 60 SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (75kHz sine wave, 2.5Vp-p, fSAMPLE = 300ksps, fSCLK = 4.8MHz) SINAD THD SFDR IMD Up to the 5th harmonic fIN1 = 73kHz, fIN2 = 77kHz -3dB point SINAD > 68dB 3.3 625 70 -80 80 76 3 250 dB dB dB dB MHz kHz s ns ns ps MHz %
4
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS--MAX1284 (Figures 1, 2, 8, 9)
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup SCLK Rise to CS Rise Hold SCLK Rise to CS Fall Ignore CS Rise to SCLK Rise Ignore SCLK Rise to DOUT Hold SCLK Rise to DOUT Valid CS Rise to DOUT Disable CS Fall to DOUT Enable CS Pulse Width High SYMBOL tCP tCH tCL tCSS tCSH tCSO tCS1 tDOH tDOV tDOD tDOE tCSW CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 10 CONDITIONS MIN 156 62 62 35 0 35 35 10 80 65 65 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MAX1284/MAX1285
TIMING CHARACTERISTICS--MAX1285 (Figures 1, 2, 8, 9)
(VDD = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup SCLK Rise to CS Rise Hold SCLK Rise to CS Fall Ignore CS Rise to SCLK Rise Ignore SCLK Rise to DOUT Hold SCLK Rise to DOUT Valid CS Rise to DOUT Disable CS Fall to DOUT Enable CS Pulse Width High SYMBOL tCP tCH tCL tCSS tCSH tCSO tCS1 tDOH tDOV tDOD tDOE tCSW CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 13 CONDITIONS MIN 208 83 83 45 0 45 45 13 100 85 85 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Tested at VDD = VDD(MIN). Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Internal reference, offset, and reference errors nulled. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to production test limitations. Note 6: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operations beyond this range, see Typical Operating Characteristics. Note 7: MAX1284 tested with 20pF on DOUT and fSCLK = 6.4MHz, 0 to 5V. MAX1285 tested with same loads, fSCLK = 4.8MHz, 0 to 3V. DOUT = full scale.
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
__________________________________________Typical Operating Characteristics
(MAX1284: VDD = +5.0V, fSCLK = 6.4MHz, MAX1285: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7F capacitor at REF, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1284/5 toc01
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.5 0.4 0.3 DNL (LSB) 0.2 0.1 0 -0.1
MAX1284/5 toc02
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1284/5 toc03
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 1k 2k 3k 4k
0.6
2.0 1.5 OFFSET ERROR (LSB) 1.0 0.5 0 -0.5 -1.0
-0.2 -0.3 -0.4 5k 0 1k 2k 3k 4k 5k DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
OFFSET ERROR vs. TEMPERATURE
MAX1284/5 toc04
GAIN ERROR vs. SUPPLY VOLTAGE
0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -2.0 -2.5 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 -40
MAX1284/5 toc05
GAIN ERROR vs. TEMPERATURE
MAX1284/5 toc06
1.8 1.6 1.4 OFFSET ERROR (LSB) 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80
1.0
1.0 0.5 GAIN ERROR (LSB) 0 -0.5 -1.0 -1.5
100
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
2.508 2.506 REFERENCE VOLTAGE (V) 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
MAX1284/5 toc07
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
2.508 REFERENCE VOLTAGE (V) 2.506 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MAX1284/5 toc08
2.510
2.510
6
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1284: VDD = +5.0V, fSCLK = 6.4MHz, MAX1285: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7F capacitor at REF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1284/5 toc09
MAX1284/MAX1285
SUPPLY CURRENT vs. TEMPERATURE
VDD = 5V, CONVERTING 2.7 SUPPLY CURRENT (mA)
MAX1284/5 toc10
3.00 2.75 SUPPLY CURRENT (mA) 2.50 2.25 2.00 1.75 1.50
CODE = 1111 1111 1111 RL = CL = 10pF
CONVERTING SCLK = 6.4MHz
3.0
2.4
VDD = 3V, CONVERTING
CONVERTING SCLK = 4.8MHz
2.1
STATIC
1.8
VDD = 5V, STATIC
VDD = 3V, STATIC
1.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -20 0 20 40 60 80 100 SUPPLY VOLTAGE (V) TEMPERATURE (C)
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME VDD AIN SHDN REF GND DOUT CS SCLK Positive Supply Voltage Sampling Analog Input, 0 to VREF range Active-Low Shutdown Input. Pulling SHDN low shuts down the device and reduces the supply current to 2A (typ). Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with 4.7F capacitor. Analog and Digital Ground Serial Data Output DOUT changes state at SCLK's rising edge High impedance when CS is high. Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high impedance. Serial Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz (MAX1284) or 4.8MHz (MAX1285). FUNCTION
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
VDD
6k DOUT 6k DGND a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL CLOAD = 20pF DOUT CLOAD = 20pF DGND
Figure 1. Load Circuits for DOUT Enable Time
VDD
6k DOUT 6k DGND a) VOH to High-Z b) VOL to High-Z CLOAD = 20pF DOUT CLOAD = 20pF DGND
Figure 2. Load Circuits for DOUT Disable Time
Detailed Description
Converter Operation
The MAX1284/MAX1285 use an input T/H and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 12-bit output. Figure 3 shows the MAX1284/MAX1285 in its simplest configuration. The internal reference is trimmed to +2.5V. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (Ps). The MAX1284/MAX1285 have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current to below 2A (typ), while pulling SHDN high puts the device into operational mode. Pulling CS low initiates a conversion that is driven by SCLK. The conversion result is available at DOUT in unipolar serial format. The serial data stream consists of three zeros, followed by the data bits (MSB first). All transitions on DOUT occur 20ns after the rising edge of SCLK. Figures 8 and 9 show the interface timing information.
Analog Input
Figure 4 illustrates the sampling architecture of the ADC's comparator. The full-scale input voltage is set by the internal reference (VREF = +2.5V). Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitor. In hold mode, the T/H switch opens and maintains a constant input to the ADC's SAR section. During acquisition, the analog input (AIN) charges capacitor CHOLD. Bringing CS low, ends the acquisition interval. At this instant, the T/H switches the input side of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing node ZERO at the comparator's input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0 within the limits of 12bit resolution. This action is equivalent to transferring a charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversion's end, the input
8
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
+5V OR +3V
10F
0.1F
1 2 3 4 4.7F
VDD
SCLK
8 7 6 5 SERIAL INTERFACE
ANALOG INPUT 0 TO VREF SHUTDOWN INPUT
AIN MAX1284 CS MAX1285 SHDN REF DOUT GND
signal to be acquired. Acquisition time is calculated by: tACQ = 9(RS + RIN) x 12pF, where R IN = 800, R S = the input signal's source impedance, and t ACQ is never less than 468ns (MAX1284) or 625ns (MAX1285). Source impedances below 2k do not significantly affect the ADCs AC performance. Higher source impedances can be used if a 0.01F capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADCs input signal bandwidth. Input Bandwidth The ADCs' input tracking circuitry has a 6MHz (MAX1284) or 3MHz (MAX1285) small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate, by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and GND, allow the input to swing from GND - 0.3V to VDD + 0.3V without damage. If the analog input exceeds 50mV beyond the supplies, limit the input current to 2mA. Internal Reference The MAX1284/MAX1285 have an on-chip voltage reference trimmed to 2.5V. The internal reference output is connected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to 800A. Bypass REF with a 4.7F capacitor. Larger capacitors increase wake-up time when exiting shutdown (see the Using SHDN to Reduce Supply Current section). The internal reference is disabled in shutdown (SHDN = 0).
MAX1284/MAX1285
Figure 3. Typical Operating Circuit
GND CAPACITIVE DAC REF AIN CHOLD 12pF
ZERO RIN 800
COMPARATOR
CSWITCH* 6pF HOLD
TRACK
AUTOZERO RAIL *INCLUDES ALL INPUT PARASITICS
Figure 4. Equivalent Input Circuit
side of C HOLD switches back to AIN, and C HOLD charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the
Serial Interface
Initialization after Power-Up and Starting a Conversion
When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7F reference bypass capacitor up to 2ms to provide adequate charge for specified accuracy. No conversions should be performed during this time.
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
To start a conversion, pull CS low. At CS's falling edge, the T/H enters its hold mode and a conversion is initiated. Data can then be shifted out serially with the external clock.
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing diagrams of Figures 8 and 9 outline serial-interface operation. A CS falling edge initiates a conversion sequence: the T/H stage holds the input voltage, the ADC begins to convert, and DOUT changes from high impedance to logic low. SCLK is used to drive the conversion process, and it shifts data out as each bit of conversion is determined. SCLK begins shifting out the data after the rising edge of the third SCLK pulse. DOUT transitions 20ns after each SCLK rising edge. The third rising clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are twelve data bits and three leading zeros, at least fifteen rising clock edges are needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing zeros at DOUT and have no effect on converter operation. Pull CS high after reading the conversion's LSB. For maximum throughout, CS can be pulled low again to initiate the next conversion immediately after the specified minimum time (tCS).
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by shutting down the MAX1284/MAX1285 between conversions. Figure 5 shows a plot of average supply current versus conversion rate. The wake-up time (tWAKE) is the time from when SHDN is deasserted to the time when a conversion may be initiated (Figure 6). This time depends on the time in shutdown (Figure 7) because the external 4.7F reference bypass capacitor loses charge slowly during shutdown and can be as long as 2ms.
10k VDD = 3V DOUT = FS RL = CL = 10pF
1k SUPPLY CURRENT (A)
100
10
1
Output Coding and Transfer Function
0.1 1 10 100 1k 10k 100k
0.1 CONVERSION RATE (ksps)
Figure 5. Supply Current vs. Conversion Rate
The data output from the MAX1284/MAX1285 is binary, and Figure 10 depicts the nominal transfer function. Code transitions occur halfway between successiveinteger LSB value VREF = +2.5V, and 1LSB = 610V or 2.5V/4096.
COMPLETE CONVERSION SEQUENCE CS tWAKE SHDN
DOUT CONVERSION 0 POWERED-UP POWERED-DOWN CONVERSION 1 POWERED-UP
Figure 6. Shutdown Sequence 10 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
1.50 REFERENCE POWER-UP DELAY (ms) CREF = 4.7F 1.25 1.00 0.75 0.50 0.25 0 0.0001
Applications Information
Connection to Standard Interfaces
The MAX1284/MAX1285 serial interface is fully compatible with SPI/QSPI and MICROWIRE (Figure 11). If a serial interface is available, set the CPU's serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 6.4MHz (MAX1284) or 4.8MHz (MAX1285). 1) Use a general-purpose I/O line on the CPU to pull CS low. Keep SCLK low. 2) Activate SCLK for a minimum of fifteen clock cycles. The first two clocks produce zeros at DOUT. DOUT output data transitions 20ns after the third SCLK rising edge and is available in MSB-first format. Observe the
MAX1284/MAX1285
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
Figure 7. Reference Power-Up vs. Time in Shutdown
CS 1 SCLK DOUT HIGH-Z HIGH-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 4 8 12 15
A/D STATE
HOLD/CONVERT ACQ
ACQUISITION
Figure 8. Interface Timing Sequence
CS
tCSW ttCSO CSO tCSS tCL tCH tCSH tCSI
SCLK tCP tDOH tDOE DOUT tDOV tDOD
Figure 9. Detailed Serial-Interface Timing
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11
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
OUTPUT CODE 11...111 11...110 11...101 FULL-SCALE TRANSITION I/O SCK MISO +3V TO +5V CS SCLK DOUT
MAX1284 MAX1285
FS = VREF - 1LSB 1LSB = VREF 4096 00...011 00...010 00...001 00...000 0 1 2 3 INPUT VOLTAGE (LSBs) FS FS - 3/2LSB b) QSPI SS SS a) SPI
CS SCK MISO +3V TO +5V
CS SCLK DOUT
MAX1284 MAX1285
Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF - 1LSB, Zero Scale (ZS) = GND
I/O
CS SCLK DOUT
SCLK to DOUT valid timing characteristic. Data can be clocked into the P on SCLK rising edge. 3) Pull CS high at or after the 15th rising clock edge. If CS remains low, trailing zeros are clocked out after the LSB. 4) With CS = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CS low. If a conversion is aborted by pulling CS high before the conversion completes, wait for the minimum acquisition time, tACQ, before starting a new conversion. CS must be held low until all data bits are clocked out. Data can be output in two bytes or continuously, as shown in Figure 8. The bytes contain the result of the conversion padded with three leading zeros and three trailing zeros.
SK SI
MAX1284 MAX1285
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1284/MAX1285
QSPI
Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1284/MAX1285 require 15 clock cycles from the P to clock out the 12 bits of data. Figure 13 shows a transfer using CPOL = 0 and CPHA = 1. The conversion result contains two zeros followed by the 12 bits of data in MSB-first formatted.
SPI and MICROWIRE
When using SPI or MICROWIRE, set CPOL = 0 and CPHA = 0. Conversion begins with a CS falling edge. DOUT goes low, indicating a conversion in progress. Two consecutive 1-byte reads are required to get the full twelve bits from the ADC. DOUT output data transitions on SCLK's rising edge and is clocked into the following P on the rising edge. The first byte contains three leading zeros, and five bits of conversion result. The second byte contains the remaining seven bits and one trailing zero. See Figure 11 for connections and Figure 12 for timing.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package.
12
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
Figure 14 shows the recommended system ground connections. Establish a single-point analog ground ("star" ground point) at GND, separate from the logic ground. Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the ADC's high-speed comparator. Bypass this supply to the single-point analog ground with 0.1F and 10F bypass capacitors. Minimize capacitor lead lengths for best supply noise rejection. To reduce the effects of supply noise, a 10 resistor can be connected as a lowpass filter to attenuate supply noise (Figure 14).
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1284/MAX1285 are measured using the endpoints method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of 1LSB or less guarantees no missing codes and a monotonic transfer function.
CS
1 SCLK
8
9
16
DOUT
HIGH-Z D11
HIGH-Z D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FIRST BYTE READ
SECOND BYTE READ
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
CS
SCLK
1
3
14
HIGH-Z DOUT
HIGH-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)
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13
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference MAX1284/MAX1285
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals.
VDD GND
SUPPLIES VDD
SINAD (dB) = 20 x log (SignalRMS/NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the effective number of bits as follows:
R* = 10 4.7F
0.1F VDD GND VDD DGND
ENOB = (SINAD - 1.76) 6.02
MAX1284 MAX1285
*OPTIONAL
DIGITAL CIRCUITRY
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 V 2 + V3 + V4 + V5 2 THD = 20 x log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd through 5th-order harmonics.
Figure 14. Power-Supply Grounding Condition
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the falling edge of CS and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component.
___________________Chip Information
TRANSISTOR COUNT: 4286 PROCESS: BiCMOS
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400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
________________________________________________________________Package Information
DIM A A1 B C D E e H h L INCHES MAX MIN 0.069 0.053 0.010 0.004 0.019 0.014 0.010 0.007 0.344 0.337 0.157 0.150 0.050 BSC 0.244 0.228 0.020 0.010 0.050 0.016 8 0 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
21-331A
MAX1284/MAX1285
E
H
D A e B
0.127mm 0.004in.
h x 45
A1
C
L
14-PIN PLASTIC SMALL-OUTLINE PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________15 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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